chipspec.c

Go to the documentation of this file.

/******************************************************************/
struct tag_chipspec chipspec[ARRAY_CHIPSPEC] = {
  /*
   * .name          = chip's name, i.e. MX25L1605D.
   * .id_JEDEC      = (MSB) 0x00, Manufacturer ID, Model ID, Device ID (LSB)
   * .chipsize      = total chipsize in bytes
   * .pagesize      = size of a page (in bytes)
   * .sizeOTP       = size of otp area
   * .cmdset        = featured commands, selection
   * .sr_is_static  = true, if status register is not initialized during power-up
   * .sr_wrmask     = status register masks, maskout unused bits of the status registers
   * .sr_bitnames   = status register bit names
   */
 
 
  /*
   * unknown chip
   * ============
   *
   *
   */
  {
    .name                 = "unknown",
    .id_JEDEC             = NOT_APPLICABLE,    
    .chipsize             = NOT_APPLICABLE,
    .pagesize             = NOT_APPLICABLE,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            ,
    .sr_is_static         = {
      0,
      0,
      0
    },
    .sr_wrmask            = {
      0,
      0,
      0
    },
    .sr_bitnames          = {
      "",
      "",
      ""
    },
  },
 
  /*
   * SST25VF016B
   * ===========
   *
   * Datasheet
   * ---------
   *
   * http://ww1.microchip.com/downloads/en/DeviceDoc/20005044C.pdf
   *
   * The JEDEC Read ID instruction is terminated by a low to high transition
   * on CE# at any time during data output. If no other command is issued
   * after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command
   * before going into Standby Mode. --> Our NOP Flag
   *
   * Notes
   * -----
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0x70, Enable SO to output programming status
   * 0x80, Disable SO to output programming status
   *
   */
  {
    .name                 = "SST25VF016B",
    .id_JEDEC             = 0x00bf2541,    
    .chipsize             = SIZE_16MBIT,
    .pagesize             = NOT_APPLICABLE,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X00_NOP) \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << X52_BE32K) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_BP) \
                            | (1 << XAD_CP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X50_EWSR) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b00000000,
      0,
      0
    },
    .sr_wrmask            = {
      0b10011100,
      0,
      0
    },
    .sr_bitnames          = {
      "BPL\tAAI\t-\tBP2\tBP1\tBP0\tWEL\tBUSY\t",
    },
  },
 
  /*
   * MX25L1605D
   * ==========
   *
   * Datasheet
   * ---------
   *
   * http://www.macronix.com/Lists/Datasheet/Attachments/4978/MX25L6405D,%203V,%2064Mb,%20v1.5.pdf
   * Version REV. 1.5, APR. 29, 2009
   *
   * Some Bits are greyed out without explication.
   * This chip seems to NOT have bits CP, BP3 in Status Register.
   *
   * Notes
   * -----
   *
   * Command XAD_CP doesn't work.
   * Bits LDSO and SOTPI in SCUR seem to be always zero.
   * Commands ENSO and EXSO don't work, is there no OTP region accessible?
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0xad, Continuously Program Mode
   * 0xb1, Enter Secured OTP
   * 0xc1, Exit Secured OTP
   * 0x2b, Read Security Register
   * 0x2f, Write Security Register
   * 0x70, Enable SO to output programming status
   * 0x80, Disable SO to output programming status
   *
   * Dual SPI:
   * 0xbb, Read Dual I/O
   * 0xef, REMS Dual I/O
   *
   */
  {
    .name                 = "MX25L1605D",
    .id_JEDEC             = 0x00c22015,    
    .chipsize             = SIZE_16MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_BP) \
                            | (1 << X02_PP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b10011100,       //according to datasheet, bit5 is non-volatile?
      0,
      0
    },
    .sr_wrmask            = {
      0b10011100,       //according to datasheet, bit5 should be writable?
      0,
      0
    },
    .sr_bitnames          = {
      "SRWD\tCP\tBP3\tBP2\tBP1\tBP0\tWEL\tWIP\t",
    },
  },
 
  /*
   * MX25L3205D
   * ==========
   *
   * Datasheet
   * ---------
   *
   * Same as MX25L1605D.
   *
   *
   * Notes
   * -----
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0xb1, Enter Secured OTP
   * 0xc1, Exit Secured OTP
   * 0x2b, Read Security Register
   * 0x2f, Write Security Register
   * 0x70, Enable SO to output programming status
   * 0x80, Disable SO to output programming status
   *
   * Dual SPI:
   * 0xbb, Read Dual I/O
   * 0xef, REMS Dual I/O
   *
   */
  {
    .name                 = "MX25L3205D",
    .id_JEDEC             = 0x00c22016,    
    .chipsize             = SIZE_32MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_BP) \
                            | (1 << X02_PP) \
                            | (1 << XAD_CP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b10111100,
      0,
      0
    },
    .sr_wrmask            = {
      0b10111100,
      0,
      0
    },
    .sr_bitnames          = {
      "SRWD\tCP\tBP3\tBP2\tBP1\tBP0\tWEL\tWIP\t",
    },
  },
 
  /*
   * MX25L6405D
   * ==========
   *
   * Datasheet
   * ---------
   *
   * Same as MX25L1605D.
   *
   *
   * Notes
   * -----
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0xb1, Enter Secured OTP
   * 0xc1, Exit Secured OTP
   * 0x2b, Read Security Register
   * 0x2f, Write Security Register
   * 0x70, Enable SO to output programming status
   * 0x80, Disable SO to output programming status
   *
   * Dual SPI:
   * 0xbb, Read Dual I/O
   * 0xef, REMS Dual I/O
   *
   */
  {
    .name                 = "MX25L6405D",
    .id_JEDEC             = 0x00c22017,    
    .chipsize             = SIZE_64MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_BP) \
                            | (1 << X02_PP) \
                            | (1 << XAD_CP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b10111100,
      0,
      0
    },
    .sr_wrmask            = {
      0b10111100,
      0,
      0
    },
    .sr_bitnames          = {
      "SRWD\tCP\tBP3\tBP2\tBP1\tBP0\tWEL\tWIP\t",
    },
  },
 
  /*
   * MX25L8005
   * =========
   *
   * Datasheet
   * ---------
   *
   * Version REV. 2.2, OCT. 23, 2008
   *
   * Clock Frequency for READ instructions: min. 1KHz
   * According to datasheet, the chip supports page programming only.
   *
   * Notes
   * -----
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0x52, Erase Block 32K (would address a 64k block instead)
   *
   */
  {
    .name                 = "MX25L8005",
    .id_JEDEC             = 0x00c22014,    
    .chipsize             = SIZE_64MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_BP) \
                            | (1 << X02_PP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b10011100,
      0,
      0
    },
    .sr_wrmask            = {
      0b10011100,
      0,
      0
    },
    .sr_bitnames          = {
      "SRWD\t-\t-\tBP2\tBP1\tBP0\tWEL\tWIP\t",
    },
  },
 
  /*
   * AT26DF161
   * =========
   *
   * Datasheet
   * ---------
   *
   * http://www.gaw.ru/pdf/Atmel/at26/AT26DF161.pdf
   *
   *
   * Notes
   * -----
   *
   * Status Register: Only bit 7 is modifyable by user.
   *
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0x3c, Read Sector Protection Registers
   *
   */
  {
    .name                 = "AT26DF161",
    .id_JEDEC             = ID_JEDEC_AT26DF161,    
    .chipsize             = SIZE_16MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X00_NOP) \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << X52_BE32K) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_PP) \
                            | (1 << X02_BP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XAB_RDP) \
                            | (1 << XB9_DP) \
                            | (1 << X36_PS) \
                            | (1 << X39_US) \
                            ,
    .sr_is_static         = {
      0b00000000,
      0,
      0
    },
    .sr_wrmask            = {
      0b10000000,
      0,
      0
    },
    .sr_bitnames          = {
      "SPRL\t-\t-\tWPP\tSWP1\tSWP0\tWEL\tBUSY\t",
      "",
      ""
    },
  },
 
  /*
   * AT26DF321
   * =========
   *
   * Datasheet
   * ---------
   *
   * Version 3633E–DFLASH–10/07
   *
   * In a certain percentage of units, the Chip Erase feature may not function
   * correctly and may adversely affect device operation. Therefore, it is
   * recommended that the Chip Erase commands (opcodes 60h and C7h) not be used.
   *
   *
   * Notes
   * -----
   *
   * Global protect/unprotect is supported via X01_WRSR & sr_bitmask 0b10111100.
   * Write 0x00111100 in order to activate global protect.
   * Write 0x00000000 in order to activate global unprotect.
   *
   * NOTE: Only bit 7 of the Status Register will be modified when using
   * the Write Status Register command.
   *
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x3c, Read Sector Protection Registers
   * 0x60, Chip Erase
   * 0xc7, Chip Erase
   * 0x0b, Read High Frequency
   *
   */
  {
    .name                 = "AT26DF321",
    .id_JEDEC             = ID_JEDEC_AT26DF321,    
    .chipsize             = SIZE_32MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << X52_BE32K) \
                            | (1 << XD8_BE64K) \
                            | (1 << X02_BP) \
                            | (1 << X02_PP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << X36_PS) \
                            | (1 << X39_US) \
                            ,
    .sr_is_static         = {
      0b00000000,
      0,
      0
    },
    .sr_wrmask            = {
      0b10000000,
      0,
      0
    },
    .sr_bitnames          = {
      "SPRL\t-\tEPE\tWPP\tSWP1\tSWP0\tWEL\tR/B\t",
      "",
      ""
    },
  },
 
  /*
   * W25X40
   * ======
   *
   * SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI
   *
   * Datasheet
   * ---------
   *
   * Publication Release Date: September 22, 2006;
   * Preliminary - Revision I
   *
   * Notes
   * -----
   *
   * Pin #WP has no effect if SRP-Bit is zero (default).
   * Other Chip Sizes: 1MBit (0xEF3011), 2MBit (0xEF3012), 8MBit (0xEF3014).
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   *
   * Dual SPI:
   * 0x3b, Fast Read Dual Output
   *
   */
  {
    .name                 = "W25X40",
    .id_JEDEC             = 0x00ef3013,    
    .chipsize             = SIZE_4MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << XD8_BE64K) \
                            | (1 << XC7_CE) \
                            | (1 << X02_PP) \
                            | (1 << X02_BP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b10111100,
      0,
      0
    },
    .sr_wrmask            = {
      0b10111100,
      0,
      0
    },
    .sr_bitnames          = {
      "SRP\t-\tTB\tBP2\tBP1\tBP0\tWEL\tBUSY\t",
    },
  },
 
  /*
   * W25X64
   * ======
   *
   * Datasheet
   * ---------
   *
   * Notes
   * -----
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   *
   */
  {
    .name                 = "W25X64",
    .id_JEDEC             = 0x00ef3017,    
    .chipsize             = SIZE_64MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << XD8_BE64K) \
                            | (1 << XC7_CE) \
                            | (1 << X02_PP) \
                            | (1 << X02_BP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b10111100,
      0,
      0
    },
    .sr_wrmask            = {
      0b10111100,
      0,
      0
    },
    .sr_bitnames          = {
      "SRP\t-\tTB\tBP2\tBP1\tBP0\tWEL\tBUSY\t",
    },
  },
 
  /*
   * SST25VF080B
   * ===========
   *
   * Datasheet
   * ---------
   *
   * Version DS20005045C
   *
   *
   * Notes
   * -----
   *
   * After power-up, the BPL bit is reset to 0.
   * Default at power-up for BP0, BP1 and BP2 is 1.
   *
   * The JEDEC Read ID instruction is terminated by a low to high transition
   * on CE# at any time during data output.
   *
   * Commands, not used
   * ------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0x70, Enable SO to output programming status
   * 0x80, Disable SO to output programming status
   *
   */
  {
    .name                 = "SST25VF080B",
    .id_JEDEC             = 0x00bf258e,    
    .chipsize             = SIZE_64MBIT,
    .pagesize             = NOT_APPLICABLE,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << X52_BE32K) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_BP) \
                            | (1 << XAD_CP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X50_EWSR) \
                            | (1 << X05_RDSR) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b00000000,
      0,
      0
    },
    .sr_wrmask            = {
      0b10011100,
      0,
      0
    },
    .sr_bitnames          = {
      "BPL\tAAI\tBP3\tBP2\tBP1\tBP0\tWEL\tBUSY\t",
    },
  },
 
  /*
   * W25Q32FV
   * ========
   *
   * V = 2.7V to 3.6V
   * Q = Green Package with QE=1 in Status Register 2
   *
   * Datasheet
   * ---------
   *
   * https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
   *
   * WARNING: If the /WP or /HOLD pins are tied directly to the power
   * supply or ground during standard SPI or Dual SPI operation, the QE
   * bit should never be set to a 1.
   *
   * Notes
   * -----
   *
   * We are not using X50_WRSR, thus using static SR bits!
   *
   * Commands, not used:
   * -------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0x50, Write Status Register Bits as Volatiles
   * 0x75, Erase/ Program Suspend
   * 0x7a, Erase/ Program Resume
   * 0x7e, Global Block Lock
   * 0x98, Global Block Unlock
   * 0x38, Enter QPI Mode
   * 0x66, Enable Reset
   * 0x99, Reset Device
   * 0x4b, Read Unique ID
   * 0x32, Quad Page Program
   * 0x5a, Read SFDP Register
   * 0x44, Erase Security Register
   * 0x42, Program Security Register
   * 0x48, Read Security Register
   * 0x36, Individual Block Lock
   * 0x39, Individual Block Unlock
   * 0x3d, Read Block Lock
   *
   * Dual SPI:
   * 0x3b, Read High Frequency Dual Output
   * 0xbb, Read High Frequency Dual I/O
   * 0x92, Manufaturer ID, Device ID, Dual I/O
   *
   * Quad SPI:
   * 0x6b, Read High Frequency Quad Output
   * 0x77, Set Burst With Wrap
   * 0xeb, Read High Frequency Quad I/O
   * 0xe7, Word Read Quad I/O
   * 0xe3, Octal Word Read Quad I/O
   * 0x94, Manufacturer ID, Device ID, Quad I/O
   * 0xff, Exit QPI Mode
   * 0xc0, Set Read Parameters
   * 0x0c, Burst Read With Wrap
   *
   */
  {
    .name                 = "W25Q32FV",
    .id_JEDEC             = 0x00ef4016,       //0x00ef6016 in QPI mode
    .chipsize             = SIZE_32MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << X52_BE32K) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_PP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X35_RDSR2) \
                            | (1 << X15_RDSR3) \
                            | (1 << X01_WRSR) \
                            | (1 << X31_WRSR2) \
                            | (1 << X11_WRSR3) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b11111100,
      0b01111011,   //S13..11 = Non-volatile OTP Writable!
      0b11100100
    },
    .sr_wrmask            = {
      0b11111100,
      0b01000011,   //S15 = SUS, is status only; S13..11 = OTP Lock Bits!
      0b11100100,
    },
    .sr_bitnames          = {
      "SRP0\tSEC\tTB\tBP2\tBP1\tBP0\tWEL\tBUSY\t",      //S7..S0
      "SUS\tCMP\tLB3\tLB2\tLB1\t-\tQE\tSRP1\t",         //S15..S8
      "HLD/RST\tDRV1\tDRV0\t-\t-\tWPS\t-\t-\t",         //S23..S16
    },
  },
 
  /*
   * W25Q64FV
   * ========
   *
   * V = 2.7V to 3.6V
   * Q = Green Package with QE=1 in Status Register 2
   *
   * Datasheet
   * ---------
   *
   * https://www.winbond.com/resource-files/w25q64fv revr 10262016.pdf
   *
   * WARNING: If the /WP or /HOLD pins are tied directly to the power
   * supply or ground during standard SPI or Dual SPI operation, the QE
   * bit should never be set to a 1.
   *
   * Notes
   * -----
   *
   * We are not using X50_WRSR, thus using static SR bits!
   *
   * Commands, not used:
   * -------------------
   *
   * Standard SPI:
   * 0x0b, Read High Frequency
   * 0x50, Write Status Register Bits as Volatiles
   * 0x75, Erase/ Program Suspend
   * 0x7a, Erase/ Program Resume
   * 0x4b, Read Unique ID
   * 0x5a, Read SFDP Register
   * 0x44, Erase Security Register
   * 0x42, Program Security Register
   * 0x48, Read Security Register
   * 0x38, Enter QPI Mode
   * 0x66, Enable Reset
   * 0x99, Reset Device
   *
   * Dual SPI:
   * 0x3b, Read High Frequency Dual Output
   * 0xbb, Read High Frequency Dual I/O
   * 0x92, Manufaturer ID, Device ID, Dual I/O
   *
   * Quad SPI:
   * 0x32, Quad Page Program
   * 0x6b, Read High Frequency Quad Output
   * 0xeb, Read High Frequency Quad I/O
   * 0xe7, Word Read Quad I/O
   * 0xe3, Octal Word Read Quad I/O
   * 0x77, Set Burst With Wrap
   * 0x94, Manufacturer ID, Device ID, Quad I/O
   * 0xc0, Set Read Parameters
   * 0x0c, Burst Read With Wrap
   * 0xff, Exit QPI Mode
   *
   */
  {
    .name                 = "W25Q64FV",
    .id_JEDEC             = 0x00ef4017,       //0x00ef6017 in QPI mode
    .chipsize             = SIZE_64MBIT,
    .pagesize             = SIZE_256,
    .sizeOTP              = NOT_APPLICABLE,
    .cmdset               = 0 \
                            | (1 << X03_READ) \
                            | (1 << X20_SE) \
                            | (1 << X52_BE32K) \
                            | (1 << XD8_BE64K) \
                            | (1 << X60_CE) \
                            | (1 << XC7_CE) \
                            | (1 << X02_PP) \
                            | (1 << X06_WREN) \
                            | (1 << X04_WRDI) \
                            | (1 << X05_RDSR) \
                            | (1 << X35_RDSR2) \
                            | (1 << X01_WRSR) \
                            | (1 << X9F_RDID) \
                            | (1 << XB9_DP) \
                            | (1 << XAB_RDP) \
                            | (1 << XAB_RES) \
                            | (1 << X90_REMS) \
                            ,
    .sr_is_static         = {
      0b11111100,
      0b01111011,
      0
    },
    .sr_wrmask            = {
      0b11111100,
      0b01000011,   //S15 = SUS, is status only; S13..11 = OTP Lock Bits
      0
    },
    .sr_bitnames          = {
      "SRP0\tSEC\tTB\tBP2\tBP1\tBP0\tWEL\tBUSY\t",      //S7..S0
      "SUS\tCMP\tLB3\tLB2\tLB1\t-\tQE\tSRP1\t",         //S15..S8
    },
  },
};