Zerocat Chipflasher  v0.4.3 (board-edition-1)
Flash free firmware to BIOS chips, kick the Manageability Engine.
Supported Devices

It is a big difference whether you attach a single SPI flash chip to the chipflasher or whether you connect a chip which is soldered onto a sysboard. In the latter case, you will have to test a real life condition - just developing according to chip’s datasheet is not sufficient. Please compare to Power Profiles.

For some chips, the block protection mechanism is not fully supported.
We focus on Standard-SPI. Dual-SPI or Quad-SPI is not implemented.

Supported Single SPI Flash Chips

Please compare to: firmware/src/chipspec.c


  • MX25L8005 (Macronix)
  • MX25L6405D (Macronix)
  • W25X64VSFIG (Winbond)
  • W25Q64FV (Winbond)


  • AT26DF321 (Atmel)

    Chip erase may be broken according to datasheet. Use block batch erase instead.

  • MX25L3205D (Macronix)
  • W25Q32FV (Winbond)


  • SST25VF016B (SST)
  • MX25L1605D (Macronix)
  • AT26DF161 (Atmel)


  • W25X40 (Winbond)

Successfully Tested Sysboards

  • AsRock E350M1 with socketed W25Q32FVDAIQ (Winbond)

    We used the 8-pin DIL socket adaptor for flashing. Then the chip was inserted onto the sysboard.

  • Gigabyte GA-G41M-ES2L Desktop Board with MX25L8005 (Macronix)
  • Intel Desktop Board D945GCLF with W25X40 (Winbond)
    You may set bit SRP in the status register to enable WP# control.
  • ThinkPad T500 with W25X64VSFIG (Winbond)
    Flashing works fine, however booting has not been tested yet.
  • ThinkPad T400
    • with MX25L6405D (Macronix) and Intel Graphic Processor
    • with MX25L3205D (Macronix) and Hybrid Graphic Processors
  • ThinkPad X230 with MX25L6405D + MX25L3205D (Macronix)
  • ThinkPad X220 with W25Q64FV (Winbond)
  • ThinkPad X200s
    We had successfully flashed one X200s some time ago, but don't remember the chip type. We believe that all types would work, but this has to be checked.
  • ThinkPad X200
    • with MX25L6405D (Macronix)
    • with W25X64VSFIG (Winbond)
  • ThinkPad X200 with AT26DF321 (Atmel)

    Chip erase may be broken according to chip’s datasheet. Use block batch erase instead.

  • ThinkPad T60 with AT26DF161 (Atmel), Intel GPU only.
    Flashing works fine although chip’s supply voltage stays around 2.5V and thus doesn't reach proper specs.
  • ThinkPad X60/X60s (32bit)
    • with SST25VF016B (SST)
    • with MX25L1605D (Macronix)
      Are we able to fully access the Macronix’ status register?

Not yet supported, but on the TODO list

These laptops are of special interest, because they have the same CPU-Chipset combination (Core Duo or Core2Duo and i945 Northbrigde) as the ThinkPad X60, which is known to lack the Manageability Engine completely. Unfortunately, these machines are not yet supported by coreboot.

Please compare to:

  • ASUS S96F/Z96F (unknown flash chip)
  • Acer Aspire One ZG5 (Winbond 25x80AVSIG)

    Winbond SPI Flash. Size is 8Mbit (1Mbyte), organized in 256 sectors à 4Kbyte, pages of 256 bytes. Status register protection bits are static, thus hardware write protection would work. Besides "Standard SPI", this chip features "Dual Output SPI".

  • Fujitsu S. Lifebook S7110 (Spansion S25FL008A)

    Spansion SPI Flash. Size is 8Mbit (1MByte). Status register protection bits are static, thus hardwired write protection would work. Note that memory is organized in 16 sectors à 512Kbit. Pages have 256 bytes.

  • Getac P470 (unknown flash chip)
  • HP/Compaq nc6320 (M25PE80)

    Micron SPI Flash. Size is 8Mbits, sectors à 4Kbyte, pages are 256 bytes. Features 16 bytes unique ID code(!). Hardware write protection should work. Features flexible software protection modes.

  • MSI Wind U100 (MX25L8005)

    Macronix SPI Flash. Already supported, but not yet tested in situ. Size is 8Mbit (1Mbyte), 256 sectors à 32Kbit (4Kbyte). Status register protection bits are static, thus hardwired write protection would work.

  • Roda Rocky III+RK886EX (SST49LF080)

    SST LPC (Low Pin Count) Flash, 32 pins. Size is 8Mbit. WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block. Features 5 GPI pins for system design flexibility.

    Note the LPC Bus is not yet supported by the zerocat chipflasher.