Documentation for “Zerocat Chipflasher” as of Sat, 29 Mar 2025 14:42:23 +0100
Repository:
Version: v2.1.6-0-c57b46eb4
Branch: master
Propeller Spin/PASM Compiler 'OpenSpin' (c)2012-2016 Parallax Inc. DBA Parallax Semiconductor.
Version 1.00.78
Compiling...
../../firmware2/src/SPIio.spin
|-SPIclock8.spin
Done.
Program size is 1368 bytes
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Zerocat Chipflasher --- Flash free firmware, kick the Management Engine.
Copyright (C) 2025 Kai Mertens
File SPIio.spin --- access chip via SPI with basic clock frequency
This file is part of Zerocat Chipflasher.
See end of file for terms of use.
******************************************************************************
# SPI Modes
Mode# CPOL (Clock Polarity) CPHA (Clock Phase)
----- --------------------- ------------------
0 0 0
1 0 1
2 1 0
3 1 1
See Figure 1 in MX25L8006E datasheet, Rev. 1.2 of Feb 10/2012, for a nice description.
* Both Modes
- Data is written on the rising edge of the clock.
- Data is read on the falling edge of the clock.
* Mode 0
The clock is active when HIGH and must be LOW at CEn transitions (polarity is 0).
Edges of clock phase 0 are taken into consideration.
(Default mode for most SPI applications and chips.)
* Mode 3
The clock is active when LOW and must be HIGH at CEn transitions (polarity is 1).
Edges of clock phase 1 are taken into consideration.
# Interface Description
Object "../../firmware2/src/SPIio" Interface:
PUB start(vboard) :
PUB set_mask_SPI(clk_driver_bits)
PUB set_mask_CEn(mask_CEn)
PUB set_mode_SPI(mode_SPI)
PUB set_mode_WP(mode_WP)
PUB poweron
PUB poweroff
PUB is_powered :
PUB on(clk_bitpattern)
PUB off
PUB CEn_low
PUB CEn_high
PUB outbits(value, n)
PUB inbits(n)
PUB WIPtest(nlimit)
PUB stop
Program: 338 Longs
Variable: 13 Longs
# Loaded Objects
* Load SPI clock object.
# Constants
* LED pins
* SPI pins (without CLK)
* IOCLOCK_CYCLES (lowest number of cycles per bit as seen in _outbits and _inbits)
* ENUM JOB_type (order matters!)
# Globals
* stack array
* cog number
* SPI power status
# Functions
_____________________
PUB start(vboard) :
Initialize global memory.
Launch _SPIio in new cog.
Return FALSE if no cog could be started, otherwise TRUE.
__________________________________
PUB set_mask_SPI(clk_driver_bits)
Set _mask_SPI: MOSI, HOLDn, WPn, and selected clocks
___________________________
PUB set_mask_CEn(mask_CEn)
Set _mask_CEn.
___________________________
PUB set_mode_SPI(mode_SPI)
Set _mode_SPI.
_________________________
PUB set_mode_WP(mode_WP)
Set _mode_WP.
____________
PUB poweron
Enable MOSFET gate, update SPI power status.
_____________
PUB poweroff
Disable MOSFET gate, update SPI_power_status.
__________________
PUB is_powered :
Retrieve SPI power status, FALSE = off, TRUE = on.
_______________________
PUB on(clk_bitpattern)
SPI mode is set up.
SPI drivers are switched on.
________
PUB off
SPI drivers go high-impedance.
____________
PUB CEn_low
WPn level is set,
then CEn goes low.
_____________
PUB CEn_high
CEn goes high via pull-up and
WPn level is restored to be high.
______________________
PUB outbits(value, n)
Send n bits of value over SPI.
______________
PUB inbits(n)
Read n bits from SPI.
____________________
PUB WIPtest(nlimit)
Poll the WIP status bit in order to check for End-of-Write.
Parameter nlimit is an estimated count number in favor of time out value.
_________
PUB stop
Stop cog.
# Data: _SPIio
******************************************************************************
Terms of Use:
Zerocat Chipflasher is free software: you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version.
Zerocat Chipflasher is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License along
with Zerocat Chipflasher. If not, see <http://www.gnu.org/licenses/>.
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