/*

  Zerocat Chipflasher --- Flash free firmware, kick the Management Engine.

  Copyright (C) 2016, 2017, 2018, 2019, 2020, 2021, 2022  Kai Mertens <kmx@posteo.net>

  This file is part of Zerocat Chipflasher.

  Zerocat Chipflasher is free software: you can redistribute it and/or
  modify it under the terms of the GNU General Public License as
  published by the Free Software Foundation, either version 3 of the
  License, or (at your option) any later version.

  Zerocat Chipflasher is distributed in the hope that it will be
  useful, but WITHOUT ANY WARRANTY; without even the implied warranty
  of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with Zerocat Chipflasher.
  If not, see <http://www.gnu.org/licenses/>.


***/


/*

  Documentation
  =============


  Brief
  -----


  File container for SPI_COMMAND_SET.


***/


# ifndef __SPI_COMMAND_SET_H__
#   define __SPI_COMMAND_SET_H__


// No Operation
#   define CMD__NOP         0x00

// Enable Write Status Register
#   define CMD__EWSR        0x50

// Write Status Register 1
#   define CMD__WRSR        0x01

// Write Status Register 2
#   define CMD__WRSR2       0x31

// Write Status Register 3
#   define CMD__WRSR3       0x11

// Write Disable
#   define CMD__WRDI        0x04

// Read Status Register 1
#   define CMD__RDSR        0x05

// Read Status Register 2
#   define CMD__RDSR2       0x35

// Read Status Register 3
#   define CMD__RDSR3       0x15

// Read Security Register, i.e. MX25L12835E
#   define CMD__RDSCUR      0x2b

// Write Security Register, i.e. MX25L12835E
#   define CMD__WRSCUR      0x2f

// Enter Macronix Secured OTP Area, i.e. MX25L12835E
#   define CMD__ENSO        0xb1

// Exit Macronix Secured OTP Area, i.e. MX25L12835E
#   define CMD__EXSO        0xc1

// Write Enable
#   define CMD__WREN        0x06

// Read JEDEC Device ID
// Some old chips (Please review ID_JEDEC_AT26DF161 and ID_JEDEC_SST25VF016B) do require
// to receive a CMD__NOP command right afterwards. The X00_NOP flag number might be
// used to flag this requirement in CHIPSPEC_t.cmdset.
#   define CMD__RDID        0x9f

// Read (at up to 25MHz)
#   define CMD__READ        0x03

// Read High Frequency (> 25MHz)
#   define CMD__READHF      0x0b

// Sector Erase (4K)
#   define CMD__SE          0x20

// Block Erase (32K)
#   define CMD__BE32K       0x52

// Block Erase (64K)
#   define CMD__BE64K       0xd8

// Full Chip Erase (0x60)
#   define CMD__CE_0X60     0x60

// Full Chip Erase (0xc7)
#   define CMD__CE_0XC7     0xc7

// Byte Program
#   define CMD__BP          0x02

// Page Program
#   define CMD__PP          0x02

// Continuous Program
#   define CMD__CP          0xad

// Deep Powerdown
#   define CMD__DP          0xb9

// Release from Deep Powerdown
#   define CMD__RDP         0xab

// Read Electronic ID
#   define CMD__RES         0xab

// Read electronic manufacturer & device ID
#   define CMD__REMS        0x90

// enable SO to output RDY/_BSY during CP-Mode
#   define CMD__ESRY        0x70

// disable SO to output RDY/_BSY during CP-Mode
#   define CMD__DSRY        0x80

// Protect Sector
#   define CMD__PS          0x36

// Unprotect Sector
#   define CMD__US          0x39

// Read Sector Protect Registers
#   define CMD__RSPR        0x3c

# endif
/* __SPI_COMMAND_SET_H__ */