/*

  Zerocat Chipflasher --- Flash free firmware, kick the Management Engine.

  Copyright (C) 2016, 2017, 2018, 2020, 2021, 2022  Kai Mertens <kmx@posteo.net>

  This file is part of Zerocat Chipflasher.

  Zerocat Chipflasher is free software: you can redistribute it and/or
  modify it under the terms of the GNU General Public License as
  published by the Free Software Foundation, either version 3 of the
  License, or (at your option) any later version.

  Zerocat Chipflasher is distributed in the hope that it will be
  useful, but WITHOUT ANY WARRANTY; without even the implied warranty
  of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with Zerocat Chipflasher.
  If not, see <http://www.gnu.org/licenses/>.


***/


/*

  Documentation
  =============


  Brief
  -----


  Propeller Pin Usage and predefined Bit Values.


***/


# ifndef __PROPPINS_H__
#   define __PROPPINS_H__


//  Board Version
//  =============
//
//  Maintain configuration token:
//
//  * enable:   "\# \t "
//  * disable:  "\/\/\# \t "


# 	 define _CFG_BOARD_V2
//# 	 define _CFG_BOARD_V1


#   ifdef _CFG_BOARD_V1
#       warning Board Version: v1
#   endif
#   ifdef _CFG_BOARD_V2
#       warning Board Version: v2
#   endif


//  Fast Addressable Pins 0..8
//  ==========================


// Chip Enable Pin #1, active low.
#   define PIN_CEn1         0

// Chip Enable Pin #0, active low.
#   define PIN_CEn0         1

// Propeller’s shift-out pin.
#   define PIN_MOSI         2

// Write Protect Pin, active low.
#   define PIN_WPn          3

// Serial Clock Pin #3
#   define PIN_SCLK3        4

// Serial Clock Pin #2
#   define PIN_SCLK2        5

// Serial Clock Pin #1
#   define PIN_SCLK1        6

// Serial Clock Pin #0
#   define PIN_SCLK0        7

// Propeller’s shift-in pin.
#   define PIN_MISO         8


//  Slow Addressable Pins
//  =====================


// This pin is used to detect whether a cable is attached to the SPI Bus Connector.
// Status is soft-linked to PIN_D3.
#   define PIN_PLUGTESTn    9

// Disable SPI bus power through PNP MOSFET, active high.
#   define PIN_PNP          10

// Hold Pin, active low.
#   define PIN_HOLDn        12

// No cable is attached to SPI Bus Connector. This LED is soft-linked to PIN_PLUGTESTn.
#   define PIN_D3           13

// Propeller’s reset pin is disabled via RST_DISABLE and execution from RAM can be
// initiated.
#   define PIN_D2           14

// Program status, emits pulse train to reflect menue’s dialogue level.
#   define PIN_D1           15

// Disable Propeller’s Reset Pin, active high.
#   ifdef _CFG_BOARD_V1
#       define RST_DISABLE      16
#   endif
#   ifdef _CFG_BOARD_V2
#       define RST_DISABLE      11
#   endif

// RS232 RX (Receive) Pin
#   define PIN_RX           31

// RS232 TX (Transmit) Pin
#   define PIN_TX           30


//  Bit Values
//  ==========


#   define BIT_D3           (1 << PIN_D3)
#   define BIT_D2           (1 << PIN_D2)
#   define BIT_D1           (1 << PIN_D1)
#   define BIT_PNP          (1 << PIN_PNP)
#   define BIT_SCLK3        (1 << PIN_SCLK3)
#   define BIT_SCLK2        (1 << PIN_SCLK2)
#   define BIT_SCLK1        (1 << PIN_SCLK1)
#   define BIT_SCLK0        (1 << PIN_SCLK0)
#   define BIT_WPn          (1 << PIN_WPn)
#   define BIT_MISO         (1 << PIN_MISO)
#   define BIT_CEn0         (1 << PIN_CEn0)
#   define BIT_CEn1         (1 << PIN_CEn1)
#   define BIT_HOLDn        (1 << PIN_HOLDn)
#   define BIT_MOSI         (1 << PIN_MOSI)
#   define BIT_PLUGTESTn    (1 << PIN_PLUGTESTn)


//  Alii
//  ====


// Alternative Macro Name for BIT_PNP.
#   define BIT_PNP_DEVICE   BIT_PNP


//  Compounds
//  =========


// Bit Mask for all available CEn Pins.
#   define CEn_AVAIL        (BIT_CEn0 | BIT_CEn1)

// Bit Mask for all available Serial Clock Pins.
#   define SCLK_AVAIL       (BIT_SCLK0 | BIT_SCLK1 | BIT_SCLK2 | BIT_SCLK3)

// Bit Mask for pins that form the SPI Bus.
#   define SPI_BUS_AVAIL    (CEn_AVAIL | BIT_MOSI | BIT_WPn | BIT_HOLDn | SCLK_AVAIL | BIT_MISO)

// Bit Mask for selected Serial Clock Pins in use.
// NOTE: We can drive the SCK line with different current setups, 4 pins are available.
// - The T500-8MB-Winbond testboard requires only one pin.
// - The X200-8MB-Winbond testboard requires three pins.
// - The X60s-2MB-SST     testboard requires only one pin.
#   define SCLK_ACTIVE      (BIT_SCLK0 | BIT_SCLK1 | BIT_SCLK2 | BIT_SCLK3)

# endif
/* __PROPPINS_H__ */