/* Zerocat Chipflasher --- Flash free firmware, kick the Management Engine. Copyright (C) 2015, 2016 kai Copyright (C) 2016, 2017, 2018, 2019, 2020, 2021, 2022 Kai Mertens This file is part of Zerocat Chipflasher. Zerocat Chipflasher is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. Zerocat Chipflasher is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with Zerocat Chipflasher. If not, see . ***/ # ifndef __CHIPSPEC_H__ # define __CHIPSPEC_H__ // Database Pointers // ================= // Number of members of the chipspec database. # define CHIPSPEC_ARRAYSIZE 15 // Block Sizes // =========== # define SIZE_0 0x00000000 # define SIZE_1 0x00000001 # define SIZE_2 0x00000002 # define SIZE_4 0x00000004 # define SIZE_8 0x00000008 # define SIZE_16 0x00000010 # define SIZE_32 0x00000020 // Common Size of OTP # define SIZE_64 0x00000040 // Usual page size # define SIZE_256 0x00000100 // Common OTP Size (byte value??) # define SIZE_512 0x00000200 # define SIZE_1K 0x00000400 // Size of 4K-sector # define SIZE_4K 0x00001000 # define SIZE_16K 0x00004000 // Size of 32K-block # define SIZE_32K 0x00008000 // Size of 64K-block # define SIZE_64K 0x00010000 // Chip size 4Mbit # define SIZE_4MBIT 0x00080000 // Chip size 8Mbit # define SIZE_8MBIT 0x00100000 // Chip size 16Mbit # define SIZE_16MBIT 0x00200000 // Chip size 32Mbit # define SIZE_32MBIT 0x00400000 // Chip size 64Mbit # define SIZE_64MBIT 0x00800000 // Chip size 128Mbit # define SIZE_128MBIT 0x01000000 // Chip size 256Mbit # define SIZE_256MBIT 0x02000000 // Typical Macronix SOTP reagion size # define SIZE_SOTP SIZE_64 // JEDEC IDs // ========= // JEDEC ID of an unknown flash chip, dummy value # define ID_JEDEC_UNKNOWN 0x00000000 // JEDEC ID of the EN25QH32 flash chip. # define ID_JEDEC_EN25QH32 0x001c7016 // JEDEC ID of the EN25QH64 flash chip. # define ID_JEDEC_EN25QH64 0x001c7017 // JEDEC ID of the AT26DF161 flash chip. # define ID_JEDEC_AT26DF161 0x001f4600 // JEDEC ID of the AT26DF321 flash chip. # define ID_JEDEC_AT26DF321 0x001f4700 // JEDEC ID of the SST25VF016 flash chip, found on X60. # define ID_JEDEC_SST25VF016B 0x00bf2541 // JEDEC ID of the SST25VF080B flash chip. # define ID_JEDEC_SST25VF080B 0x00bf258e // JEDEC ID of the MX25L8005 flash chip. # define ID_JEDEC_MX25L8005 0x00c22014 // JEDEC ID of the MX25L1605D and MX25L1606E flash chips. // This ID matches multiple chips, the MX25L1605D and MX25L1606E for instance. Their datasheets have // been reviewed carefully, and congruent specifications are now used within chipspec, thus // using one chip definition only. # define ID_JEDEC_MX25L1605D_06E 0x00c22015 // JEDEC ID of the MX25L3205D and MX25L3206E flash chips. // This ID matches multiple chips, the MX25L3205D and MX25L3206E for instance. Their datasheets have // been reviewed carefully, and congruent specifications are now used within chipspec, thus // using one chip definition only. # define ID_JEDEC_MX25L3205D_06E 0x00c22016 // JEDEC ID of the MX25L6405D, MX25L6406E and MX25L6445E flash chips. // This ID matches multiple chips, the MX25L6405D, MX25L6406E and MX25L6445E for instance. Their // datasheets have been reviewed carefully, and congruent specifications are now used within // chipspec, thus using one chip definition only. # define ID_JEDEC_MX25L6445E_06E_05D 0x00c22017 // JEDEC ID of the MX25L12835E flash chip. # define ID_JEDEC_MX25L12835E 0x00c22018 // JEDEC ID of the W25X40 flash chip. # define ID_JEDEC_W25X40 0x00ef3013 // JEDEC ID of the W25X64 flash chip. # define ID_JEDEC_W25X64 0x00ef3017 // JEDEC ID of the W25Q32FV flash chip. # define ID_JEDEC_W25Q32FV 0x00ef4016 // JEDEC ID of the W25Q64FV flash chip. # define ID_JEDEC_W25Q64FV 0x00ef4017 // Read Commands // ============= // SPI Read Command (0x03) flag number. # define X03_READ 0 // SPI Fast Read Command (0x0b) flag number. # define X0B_READHF 1 // Program and Erase Commands // ========================== // SPI 4K Sector Erase Command (0x20) flag number. # define X20_SE 2 // SPI 32K Block Erase Command (0x52) flag number. # define X52_BE32K 3 // SPI 64K block Erase Command (0xd8) flag number. # define XD8_BE64K 4 // SPI Chip Erase Command (0x60) flag number. # define X60_CE 5 // SPI Chip Erase Command (0xc7) flag number. # define XC7_CE 6 // SPI Page Program Command (0x02) flag number. # define X02_PP 7 // SPI Continuous Program Command (0xad) flag number. # define XAD_CP 8 // SPI Byte Program Command (0x02) flag number. # define X02_BP 9 // Protection Commands // =================== // SPI Write Enable Command (0x06) flag number. # define X06_WREN 10 // SPI Write Disable Command (0x04) flag number. # define X04_WRDI 11 // SPI Enable Write Status Register Command (0x50) flag number. # define X50_EWSR 12 // Status Register Commands // ======================== // SPI Read Status Register Command (0x05) flag number. # define X05_RDSR 13 // SPI Write Status Register Command (0x01) flag number. # define X01_WRSR 14 // If this flag number is set, a CMD__NOP is send to the device after CMD__RDID. # define X00_NOP 15 // Miscellaneous Commands // ====================== // SPI Read JEDEC Manufacturer and Device ID (3 Databytes) Command (0x9f) flag number. # define X9F_RDID 16 // SPI Enter Deep Powerdown Command (0xb9) flag number. # define XB9_DP 17 // SPI Release from Deep Powerdown Command (0xab) flag number. # define XAB_RDP 18 // Some Extras // =========== // SPI Read Electronic Signature (1 Databyte) Command (0xab) flag number. # define XAB_RES 19 // SPI Read Manufacturer and Device ID (2 Databytes) Command (0x90) flag number. # define X90_REMS 20 // SPI Read Sector Protection Registers Command (0x3c) flag number. # define X3C_RSPR 21 // SPI Protect 4K Sector Command (0x36) flag number. # define X36_PS 22 // SPI Unprotect 4K Sector Command (0x39) flag number. # define X39_US 23 // SPI Enable Ready at Pin Command (0x70) flag number. //'~ # define X70_ESRY 24 // SPI Disable Ready at Pin Command (0x80) flag number. //'~ # define X80_DSRY 25 // SPI Read Status Register 2 Command (0x35) flag number. # define X35_RDSR2 26 // SPI Read Status Register 3 Command (0x15) flag number. # define X15_RDSR3 27 // SPI Write Status Register 2 Command (0x31) flag number. # define X31_WRSR2 28 // SPI Write Status Register 3 Command (0x11) flag number. # define X11_WRSR3 29 // SPI Read Security Register Command (0x2b) flag number. # define X2B_RDSCUR 30 // SPI Write Security Register Command (0x2f) flag number. # define X2F_WRSCUR 31 // Enter Secured OTP (Macronix) Command (0xb1) flag number. # define XB1_ENSO 24 //check X70_ESRY // Leave Secured OTP (Macronix) Command (0xc1) flag number. # define XC1_EXSO 25 //check X80_DSRY // Basic SPI Commands // ================== // Basic SPI Command Set flag numbers. # define BASIC_SPI 0 \ | (1 << X01_WRSR) \ | (1 << X03_READ) \ | (1 << X04_WRDI) \ | (1 << X05_RDSR) \ | (1 << X06_WREN) \ | (1 << X20_SE) \ | (1 << X9F_RDID) \ | (1 << XD8_BE64K) // Types // ===== // Chip specifications, provided within the source code. // In case the JEDEC ID of your target board’s chip is not part of the database, // you might study the chip’s datasheet and enrich the chipspec.c database file. // However, as RAM is running out on the Propeller, this is a critical action. Maybe // you better replace one database entry instead, so that CHIPSPEC_ARRAYSIZE won't grow. // struct CHIPSPEC_t { const unsigned int id_JEDEC; //!< If not applicable or unknown, flag number X9F_RDID should be cleared in cmdset. char names[20]; //!< Chip names, i.e. “MX25L1605D” const unsigned int size; //!< Size of the chip. const unsigned int cmdset; //!< Command register, holding SPI command flags in respect to SPI_COMMAND_FLAGS. char * bits[4]; //!< Bit names of chip registers. const unsigned char is_writable[4]; //!< Register Bit Info: writable (1) or read only (0)? const unsigned char is_static[4]; //!< Register Bit Info: static (1) or volatile (0)? const unsigned char is_otp[4]; //!< Register Bit Info: one time programmable? }; # endif /* __CHIPSPEC_H__ */