/*

  Zerocat Chipflasher --- Flash free firmware, kick the Management Engine.

  Copyright (C) 2016, 2017, 2018, 2020, 2021, 2022  Kai Mertens <kmx@posteo.net>

  This file is part of Zerocat Chipflasher.

  Zerocat Chipflasher is free software: you can redistribute it and/or
  modify it under the terms of the GNU General Public License as
  published by the Free Software Foundation, either version 3 of the
  License, or (at your option) any later version.

  Zerocat Chipflasher is distributed in the hope that it will be
  useful, but WITHOUT ANY WARRANTY; without even the implied warranty
  of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with Zerocat Chipflasher.
  If not, see <http://www.gnu.org/licenses/>.


***/


/*

  Documentation
  =============


  Brief
  -----


  File container for Module SPI_FLASH_BITS.


***/


# ifndef __SPI_FLASH_BITS_H__
#   define __SPI_FLASH_BITS_H__


//  Status Register Bits
//  ====================
//
//
//  most common, but names may vary


// Status Register Write Disable
#   define SRWD             0x80

// Continuous Program Mode
#   define CPM              0x40

// Block Protect 3
#   define BP3              0x20

// Block Protect 2
#   define BP2              0x10

// Block Protect 1
#   define BP1              0x08

// Block Protect 0
#   define BP0              0x04

// Write Enable Latch
#   define WEL              0x02

// Write In Progress
#   define WIP              0x01


//  Security Register
//  =================
//
//
//  Available on some Macronix types.


// Lock-down Block Protection Bits (can't be reset!).
#   define WPSEL            0x80

// Lock-down Secured OTP (can't be reset!).
#   define LDSO             0x02

// Secured OTP Indicator Bit.
// Indicates whether SOTP had been locked by factory (1) or customer (0).
#   define SOTPI            0x01

# endif
/* __SPI_FLASH_BITS_H__ */