chipflasher/html/SPI-command-set_8h_source.html

/******************************************************************/

#ifndef __SPI_COMMAND_SET_H__

#define __SPI_COMMAND_SET_H__


#define CMD__NOP          0x00

#define CMD__EWSR         0x50

#define CMD__WRSR         0x01

#define CMD__WRSR2        0x31

#define CMD__WRSR3        0x11

#define CMD__WRDI         0x04

#define CMD__RDSR         0x05

#define CMD__RDSR2        0x35

#define CMD__RDSR3        0x15

#define CMD__WREN         0x06

#define CMD__RDID         0x9f

#define CMD__READ         0x03

#define CMD__READHF       0x0b

#define CMD__SE           0x20

#define CMD__BE32K        0x52

#define CMD__BE64K        0xd8

#define CMD__CE_0X60      0x60

#define CMD__CE_0XC7      0xc7

#define CMD__BP           0x02

#define CMD__PP           0x02

#define CMD__CP           0xad

#define CMD__DP           0xb9

#define CMD__RDP          0xab

#define CMD__RES          0xab

#define CMD__REMS         0x90

#define CMD__ESRY         0x70

#define CMD__DSRY         0x80

#define CMD__PS           0x36

#define CMD__US           0x39

#define CMD__RSPR         0x3c


#endif

/* __SPI_COMMAND_SET_H__ */